In NAND flash memory systems, a multilevel technique enabling to store data of two or more bits in one memory cell is widely used to cut bit cost. Furthermore, downscaling of memory cells has been advanced to reduce the chip size. Under these circumstances, widening of threshold distributions caused by interference between adjacent cells (inter-cell interference effect) is not negligible. The inter-cell interference effect is a phenomenon that the threshold voltage of a memory cell to which data is already written shifts by writing data to an adjacent memory cell. The inter-cell interference effect possibly causes widening of threshold voltage distributions of memory cells and degradation of reliability of reading data.
As measures against the problem, there are known the following techniques. According to one technique (Technique 1), the inter-cell interference effect is suppressed by changing a page write order. According to another technique (Technique 2), data is read from a word line adjacent to a read-target word line, and a read level at a time of reading data from the read-target word line is changed based on the data read from the adjacent word line, thereby correcting the inter-cell interference effect derived from the adjacent memory cell connected to the adjacent word line.